The present invention relates generally to multiprocessor systems, and more specifically to data transfer between a main memory and an external storage unit of a multiprocessor system.
With current multiprocessor systems, each processor receives a report from an external mass storage unit whenever an event, such as data transfer error, interface error, power turn-on or turn-off, overvoltage, and an abnormal temperature condition occurs, and interrupts its job without paying attention to whatever kind of the report it has received or to whatever kind of job it is currently processing. This indiscriminate interrupt scheme results in an increase in the processor overhead, and hence a decrease in the overall efficiency of a multiprocessor system.